(1) Field of the Invention
The present invention relates to a timing phase control apparatus and a timing phase control method which are particularly suitable for use in a modem used for very high speed data transmission employing a metallic line.
(2) Description of the Related Art
In general, a modem (modulator/demodulator) is used to transmit data over a phone line, a leased line, an in-plant metallic line, and so forth. In recent years, a more inexpensive higher-speed modem has been required in the modem market. In order to meet the market requirements, digital signal processing of a DSP (Digital Signal Processor) is used to reduce hardware as much as possible, resulting in commercial availability of a more inexpensive higher-speed modem.
FIG. 22 is a block diagram showing one illustrative system for data communication through the modem. In a data communication system 100 shown in FIG. 22, a host processor 101 is connected to a metallic line 105 through a modem (modulator/demodulator) 102 serving as a master (ST2, ST1), and a terminal 104 is connected to the metallic line 105 through a modem 103 serving as a slave (RT).
Here, the metallic line 105 is a line including metal wire such as copper wire, and data can be transmitted over the metallic line 105 at very high speed of, for example, about 1.5 Mbps. The metallic line 105 can be connected to the host processor 101 and the terminal 104 for use in processing of a massive amounts of data such as image information, and transmission and reception of the data.
Further, the modems 102, 103 chiefly include an MPU (Microprocessor Unit), an A/D converter, a D/A converter, a low-pass filter, and the DSP. Receive data is processed through, for example, gray/natural transformation, summation, signal point generation, roll off filter processing, and modulation processing, and is thereafter converted through digital-to-analog conversion to be transmitted to the metallic line 105. On the other hand, a received modulated analog signal is converted into a digital signal, and is thereafter processed through signal processing such as demodulation, decimation processing, timing phase control, and decision, resulting in reproduction of the data. Moreover, the reproduced data is output to the host processor 101 or the terminal 104.
Meanwhile, the modem 102 on the side of the host processor 101 includes one part (ST2) operated by an internally generating clock, and another part (ST1) operated depending upon a clock signal from the host processor 101. The modem 103 serving as the slave (RT) on the side of the terminal 104 is operated by a clock signal generated depending upon a clock component in a signal from the modem 102.
Here, the timing phase control is made to the receive data by the slave modem 103 appropriately using a timing PLL (Phase Locked Loop) in a DSP 103b. However, in the master modem 102, the timing phase control is made through filter processing by a timing phase control filter.
That is, as shown in FIG. 23, the master modem 102 includes a timing extracting portion 102A to extract a timing phase of a receive signal, a phase deciding portion (TIMJ) 102B to decide the timing phase extracted in the timing extracting portion 102A, and a timing phase control filter (TMA) 102C to make a timing phase control depending upon the result of decision in the phase deciding portion 102B.
For example, the phase deciding portion 102B decides in which of 32 areas obtained by equally dividing a range of -180.degree. to +180.degree. the timing phase extracted in the timing extracting portion 102A is.
Further, the timing phase control filter 102C includes, for example, a transversal filter 102a for a 29-stage tap operation as shown in FIG. 24.
Here, in the transversal filter 102a shown in FIG. 24, reference numerals 102a-1 to 102a-29 respectively designate delay portions (X.sub.1 to X.sub.29) to delay receive signals (DEM1R-4R and DEM1I-4I) by a quarter tap.
Further, reference numerals 102b-1 to 102b-29 respectively indicate multipliers to multiply receive taps delayed in the delay portions 102a-1 to 102a-29 by tap coefficients C.sub.1 to C.sub.29, and 102c is a total sum calculating portion to calculate and output the total sum of signals obtained by the tap operation in the multipliers 102b-1 to 102b-29.
Moreover, reference numeral 102d denotes a rounding portion to round an operation result from the total sum calculating portion 102c, and output the result as a timing phase control result.
Meanwhile, the transversal filter 102a is provided with a coefficient information memory 102e containing data of the respective tap coefficients C.sub.1 to C.sub.29 with phase decision information as address information. Thus, the coefficient information memory 102e can output a corresponding tap coefficient to the transversal filter 102a depending upon a phase decision result (TIMJL of, for example, 5 bits) from the phase deciding portion 102B.
Moreover, FIG. 25 is a diagram showing a part of the coefficient information memory 102e. In FIG. 25, a range of 360.degree. is divided into 32 areas (at 11.25 degree intervals), thereby showing the tap coefficients C.sub.1 set for each of phase information in the 32 areas. Consequently, the actual coefficient information memory 102e contains information about the tap coefficients C.sub.2 to C.sub.29 as well as the information about the tap coefficients C.sub.1 as shown in FIG. 25.
That is, depending upon the phase decision result (for example, 5-bit data) from the phase deciding portion 102B, the timing phase control filter 102C can derive from the coefficient information memory 102e all the tap coefficients C.sub.1 to C.sub.29 to be multiplied by the receive taps in the multipliers 102b-1 to 102b-29.
In the modem 102 shown in FIG. 22, the timing phase control is made by the digital signal processing of the DSP, thereby providing a more inexpensive higher-speed modem in recent years. In order to realize significant cost reduction, it is necessary to reduce the number of mounted DSPs.
However, in the modem 102 as shown in FIG. 22, values of the tap coefficients of the timing phase control filter 102C are previously held in the table 102e as table data.
As the modem has a higher transmission speed, an error of the timing phase must be made smaller. It is thereby necessary to improve an accuracy of the tap coefficient of the timing phase control filter. This case produces an increase in amount of table data serving as tap coefficient data to be contained in the table 102e, resulting in a problem in that the number of DSPs is increased.
For example, when the timing phase control filter 102C includes the 29-stage transversal filter 102a as described above, the table 102e must contain all the tap coefficients according to 32 types of decision results. For the tap coefficient C.sub.1 used for the tap operation in the multiplier 102b-1, it is required to store values as shown in FIG. 25 according to the phase decision result.